To meet the requirements of the computer and telecommunications industries, power supply technology is moving In a direction of increased switching frequency and reduced form factor. Circuit designers depend on distributed power architecture to support low-voltage processors by bringing power supplies closer to the processor. As the power demands of various circuits increase, power dissipation becomes a significant obstacle to improving circuit efficiency. Therefore, analyzing such power dissipation to contain power losses is highly desirable.
The primary function of the power supply is to provide a predetermined constant output voltage against the variation of input voltage, as well as the dynamically changing output load. The current flowing through the switching device may vary significantly, due to output load, operating temperature, and surge current. Specifically, the switching device is subjected to high current levels during the process of load regulation. The load regulation process undergoes several switching cycles before reaching a steady-state condition. Moreover, the switching device is subjected to maximum power dissipation during the switching cycle from an “ON” state to an “OFF” state and from the OFF state to the ON state. Therefore, power-supply circuit designers would attempt to optimize the switching circuit of the switch-mode power supply by reducing the switching current and minimizing the power loss associated with such switching current, as well as ensure that the switching device does not experience a “break even” value of instantaneous power, which could potentially damage the switching device.
In order to optimize the switching circuits of switch-mode power supplies (SMPS), there is a need in the art for the circuit designers to monitor the instantaneous power during the regulation process.